1 ?2004 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 2002, rev. l cat5112 32-tap digitally programmable potentiometer (dpp?) with buffered wiper features 32-position linear taper potentiometer non-volatile nvram wiper storage; buffered wiper low power cmos technology single supply operation: 2.5v-6.0v increment up/down serial interface resistance values: 10k ?, ?, ?, ?, ?, 50k ? ? ? ? ? and 100k ? ? ? ? ? available in pdip, soic, tssop and msop p ackages applications automated product calibration remote control adjustments offset, gain and zero control tamper-proof calibrations contrast, brightness and volume controls motor controls and feedback systems programmable analog functions system values without effecting the stored setting. wiper-control of the cat5112 is accomplished with three input control pins, cs , u/ d , and inc . the inc input increments the wiper in the direction which is determined by the logic state of the u/ d input. the cs input is used to select the device and also store the wiper position prior to power down. the digitally programmable potentiometer can be used as a buffered voltage divider. for applications where the potentiometer is used as a 2-terminal variable resistor, please refer to the cat5114. the buffered wiper of the cat5112 is not compatible with that appli- cation. dpps bring variability and programmability to a broad range of applications and are used primarily to control, regulate or adjust a characteristic or parameter of an analog circuit. functional diagram description the cat5112 is a single digitally programmable potentiometer (dpp ) designed as a electronic replacement for mechanical potentiometers and trim pots. ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. the cat5112 contains a 32-tap series resistor array connected between two terminals r h and r l . an up/ down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, r wb . the cat5112 wiper is buffered by an op amp that operates rail to rail. the wiper setting, stored in non-volatile nvram memory, is not lost when the de- vice is powered down and is automatically recalled when power is returned. the wiper can be adjusted to test new electronic potentiometer implementation r h + r wb r l cs + inc u /d control and memory v cc r r r wb h l v ss power on recall > h a l o g e n f r e e tm l e a d f r e e
cat5112 2 doc. no. 2002, rev. l of the cat5112 and is active low. when in a high state, activity on the inc and u/ d inputs will not affect or change the position of the wiper. device operation the cat5112 operates like a digitally controlled potentiometer with r h and r l equivalent to the high and low terminals and r wb equivalent to the mechanical potentiometer's wiper. there are 32 available tap posi- tions including the resistor end points, r h and r l . there are 31 resistor elements connected in series between the r h and r l terminals. the wiper terminal is connected to one of the 32 taps and controlled by three inputs, inc , u/ d and cs . these inputs control a five-bit up/down counter whose output is decoded to select the wiper position. the selected wiper position can be stored in nonvolatile memory using the inc and cs inputs. with cs set low the cat5112 is selected and will respond to the u/ d and inc inputs. high to low transitions on inc wil increment or decrement the wiper (depending on the state of the u/ d input and five- bit counter). the wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. the value of the counter is stored in nonvolatile memory whenever cs transitions high while the inc input is also high. when the cat5112 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. when power is restored, the contents of the memory are recalled and the counter is set to the value stored. with inc set low, the cat5112 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. this allows the system to always power up to a preset value stored in nonvolatile memory. pin descriptions inc inc inc inc inc : increment control input the inc input (on the falling edge) moves the wiper in the up or down direction determined by the condition of the u/ d input. u/ d d d d d : up/down control input the u/ d input controls the direction of the wiper movement. when in a high state and cs is low, any high- to-low transition on inc will cause the wiper to move one increment toward the r h terminal. when in a low state and cs is low, any high-to-low transition on inc will cause the wiper to move one increment towards the r l terminal. r h: high end potentiometer terminal r h is the high end terminal of the potentiometer. it is not required that this terminal be connected to a potential greater than the r l terminal. voltage applied to the r h terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r wb : wiper potentiometer terminal (buffered) r wb is the buffered wiper terminal of the potentiometer. its position on the resistor array is controlled by the control inputs, inc , u/ d and cs . r l : low end potentiometer terminal r l is the low end terminal of the potentiometer. it is not required that this terminal be connected to a potential less than the r h terminal. voltage applied to the r l terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r l and r h are electrically interchangeable. cs cs cs cs cs : chip select the chip select input is used to activate the control input pin functions pin name function inc increment control u/ d up/down control r h potentiometer high terminal gnd ground r wb buffered wiper terminal r l potentiometer low terminal cs chip select v cc supply voltage pin configuration pdip package (p, l) tssop package (u, y) msop package (r, z) inc v cc cs r l r wb u /d r h gnd 1 2 3 4 8 7 6 5 cs inc v cc r l r wb u /d r h gnd 1 2 3 4 8 7 6 5 v cc r l r wb gnd r h inc u/ d cs 1 2 3 4 8 7 6 5 cs inc v cc r l r wb u /d r h gnd 1 2 3 4 8 7 6 5 soic package (s, v)
cat5112 3 doc. no. 2002, rev. l power supply symbol parameter conditions min typ max units v cc operating voltage range 2.5 6.0 v i cc1 supply current (increment) v cc = 6v, f = 1mhz, i w =0 200 a v cc = 6v, f = 250khz, i w =0 100 i cc2 supply current (write) programming, v cc = 6v 1ma v cc = 3v 500 a isb 1 (2) supply current (standby) cs=v cc -0.3v 75 150 a u/d, inc=v cc -0.3v or gnd operating modes absolute maximum ratings supply voltage v cc to gnd -0.5v to +7v inputs cs to gnd -0.5v to v cc +0.5v inc to gnd -0.5v to v cc +0.5v u/ d to gnd -0.5v to v cc +0.5v r h to gnd -0.5v to v cc +0.5v r l to gnd -0.5v to v cc +0.5v r wb to gnd -0.5v to v cc +0.5v operating ambient temperature commercial ( c or blank suffix) 0 c to +70 c industrial ( i suffix) -40 c to +85 c junction temperature +150 c storage temperature -65 c to +150 c lead soldering (10 sec max) +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is not implied. device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. notes: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) latch-up protection is provided for stresses up to 100ma on address and data pins from 1v to v cc + 1v (3) i w =source or sink (4) these parameters are periodically sampled and are not 100% tested. r l c l c h r h c w r wb r wi potentiometer equivalent circuit inc cs u/d operation high to low low high wiper toward h high to low low low wiper toward l high low to high x store wiper position low low to high x no store, return to standby x high x standby reliability characteristics symbol parameter test method min typ max units v zap (1) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (1)(2) latch-up jedec standard 17 100 ma t dr data retention mil-std-883, test method 1008 100 years n end endurance mil-std-883, test method 1003 1,000,000 stores dc electrical characteristics: v cc = +2.5v to +6.0v unless otherwise specified symbol parameter conditions min typ max units i ih input leakage current v in = v cc 10 a i il input leakage current v in = 0v 10 a v ih1 ttl high level input voltage 4.5v v cc 5.5v 2 v cc v v il1 ttl low level input voltage 0 0.8 v v ih2 cmos high level input voltage 2.5v v cc 6v v cc x 0.7 v cc + 0.3 v v il2 cmos low level input voltage -0.3 v cc x 0.2 v logic inputs
cat5112 4 doc. no. 2002, rev. l symbol parameter conditions min typ max units r pot potentiometer resistance -10 device 10 -50 device 50 k ? -00 device 100 pot resistance tolerance 20 % v rh voltage on r h pin 0 v cc v v rl voltage on r l pin 0 v cc v resolution 1 % inl integral linearity error i w 2 a 0.5 1 lsb dnl differential linearity error i w 2 a 0.25 0.5 lsb r out buffer output resistance .05v cc v wb .95v cc , v cc =5v 1 ? i out buffer output current .05v cc v wb .95v cc , v cc =5v 3 ma tc rpot tc of pot resistance 300 ppm/ ? c tc ratio ratiometric tc tbd ppm/ ? c r iso isolation resistance tbd ? c rh /c rl /c rw potentiometer capacitances 8/8/25 pf fc frequency response passive attenuator, 10k ? 1.7 mhz v wb(swing) output voltage range i out 100 a, v cc =5v 0.01v cc .99v cc potentiometer parameters
cat5112 5 doc. no. 2002, rev. l v cc range 2.5v v cc 6v input pulse levels 0.2v cc to 0.7v cc input rise and fall times 10ns input reference levels 0.5v cc ac conditions of test (1) typical values are for t a =25 ? c and nominal supply voltage. (2) this parameter is periodically sampled and not 100% tested. (3) mi in the a.c. timing diagram refers to the minimum incremental change in the w output due to a change in the wiper position . cs inc u /d r w t ci t cyc t il mi (3) 90% 90% 10% (store) t f t r t iw tid tdi t ih t cph t ic symbol parameter min typ (1) max units t ci cs to inc setup 100 ns t di u/ d to inc setup 50 ns t id u/ d to inc hold 100 ns t il inc low period 250 ns t ih inc high period 250 ns t ic inc inactive to cs inactive 1 s t cph cs deselect time (no store) 100 ns t cph cs deselect time (store) 10 ms t iw inc to v out change 15 s t cyc inc cycle time 1 s t r, t f (2) inc input rise and fall time 500 s t pu (2) power-up to wiper stable 1 msec t wr store cycle 510ms ac operating characteristics: v cc = +2.5v to +6.0v, v h = v cc , v l = 0v , unless otherwise specified a. c. timing
cat5112 6 doc. no. 2002, rev. l ordering information prefix device # suffix 5112 product number cat optional company id i -10 resistance -10: 10kohms -50: 50kohms -00: 100kohms temperature range blank = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) 5112: buffered 5114: unbuffered s package p: pdip s: soic u: tssop r: msop l: pdip (lead free, halogen free) v: soic (lead free, halogen free) y: tssop (lead free, halogen free) z: msop (lead free, halogen free) te13 tape & reel soic: 2000/reel tssop: 2000/reel msop: 2500/reel
cat5112 7 doc. no. 2002, rev. l notes: (1) the device used in the above example is a cat5112 si-10te13 (soic, 10k ohms, industrial temperature, tape & reel) catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the company s corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 2002 revison: l issue date: 4/12/04 type: final revision history date rev. reason 3/10/2004 j updated potentiometer parameters 3/29/2004 k changed green package marking for soic from w to v 4/12/2004 l updated reel ordering information
|
